The present invention relates to a semiconductor memory device including memory and logic circuits on the same substrate, and also relates to a method for fabricating a device of that type.
In recent years, a so-called xe2x80x9chybrid devicexe2x80x9d of the type including memory and logic circuits on the same substrate has been researched and developed vigorously to further increase the operating speed and further improve the performance of a semiconductor memory device.
On the other hand, a technique of forming a xe2x80x9cpoly-metal gatexe2x80x9d as a gate electrode for a transistor by stacking polysilicon and metal films one upon the other is now expected to play a key role in further downsizing and enhancing the performance of a semiconductor integrated circuit device. Accordingly, the implementation of a hybrid device including poly-metal gates is waited for in the art.
Hereinafter, a known method for fabricating a semiconductor memory device will be described with reference to the accompanying drawings. FIGS. 10A through 10L illustrate cross-sectional structures corresponding to respective process steps for fabricating a semiconductor memory device including poly-metal gates in memory and logic circuit sections.
First, as shown in FIG. 10A, isolation regions 102 are defined in a semiconductor substrate 101 of silicon by embedding silicon dioxide in its surface regions. As a result, multiple active regions, including memory and logic circuit sections 100 and 200 illustrated in FIG. 10A, are defined. Thereafter, tunnel insulating and first polysilicon films 103 and 104 are deposited to respective thicknesses of about 9 nm and about 250 nm over the substrate 101.
Next, as shown in FIG. 10B, a capacitive insulating film 105 is formed on the first polysilicon film 104 and then the tunnel insulating, first polysilicon and capacitive insulating films 103, 104 and 105 are patterned to remove their parts located in the logic circuit section 200.
Then, as shown in FIG. 10C, a gate insulating film 106 is formed on part of the surface of the substrate 101 that has been exposed in the logic circuit section 200. Subsequently, a second polysilicon film 107 is deposited to a thickness of about 100 nm over the substrate 101 and then doped with phosphorus (P+) ions by an ion implantation process.
Next, as shown in FIG. 10D, a metal film 108 of tungsten, for example, and a first silicon dioxide film 109 are deposited in this order to respective thicknesses of about 150 nm and about 100 nm over the second polysilicon film 107.
Thereafter, as shown in FIG. 10E, the multilayer structure consisting of the tunnel insulating, first polysilicon, capacitive insulating, second polysilicon, metal and first silicon dioxide films 103, 104, 105, 107, 108 and 109 are dry-etched while being masked with a resist pattern 110. The resist pattern 110 defined on the first silicon dioxide film 109 covers not only part of the memory circuit section 100 where a gate electrode should be formed for the memory circuit but also the entire logic circuit section 200. In this manner, a gate electrode 111 for memory circuit (which will be herein called a xe2x80x9cmemory gate structurexe2x80x9d) is formed.
Subsequently, as shown in FIG. 10F, the resist pattern 110 is removed and then source/drain regions 112 and 113 are defined in the substrate 101 using the memory gate structure 111 as a mask.
Then, as shown in FIG. 10G, the multilayer structure consisting of the gate insulating, second polysilicon, metal and first silicon dioxide films 106, 107, 108 and 109 are dry-etched while being masked with a resist pattern 114. The resist pattern 114 defined on the first silicon dioxide film 109 covers not only part of the logic circuit section 200 where a gate electrode should be formed for the logic circuit but also the entire memory circuit section 100. In this manner, a gate electrode 115 for logic circuit (which will be herein called a xe2x80x9clogic gate structurexe2x80x9d) is formed.
Subsequently, as shown in FIG. 10H, arsenic (As+) ions are implanted into the substrate 101 using the resist pattern 114 as a mask, thereby defining light-doped source/drain regions (which will be herein called xe2x80x9cLDD regionsxe2x80x9d simply) 116 and 117 in the substrate 101.
Next, as shown in FIG. 10I, after the resist pattern 114 has been removed, a second silicon dioxide film is deposited over the substrate 101 and then etched back, thereby forming sidewall insulating films 118a and 118b over the memory and logic gate structures 111 and 115, respectively.
Thereafter, as shown in FIG. 10J, a resist pattern 119 is defined to cover the memory circuit section 100 and then As+ ions are implanted into the substrate 101 using the resist pattern 119, logic gate structure 115 and sidewall insulating film 118b as a mask. In this manner, source/drain regions 120 and 121 are defined for the logic circuit.
Subsequently, as shown in FIG. 10K, the resist pattern 119 is removed and then a cobalt film is deposited over the substrate 101 and annealed so that the cobalt film deposited reacts with exposed parts of the substrate 101. In this manner, a silicide layer 122 is formed on the exposed parts of the substrate 101.
Finally, as shown in FIG. 10L, an interlevel dielectric film 123 of silicon dioxide is deposited over the substrate 101 and then contacts 124 are formed in the interlevel dielectric film 123 so as to make electrical contact with the source/drain regions 112 and 113 and 120 and 121 for the memory and logic circuits. As a result, a semiconductor memory device is completed.
In the known semiconductor memory device, however, the tunnel insulating film 103 of the memory gate structure 111 might show inferior reliability.
Specifically, when the source/drain regions 112 and 113 are defined for the memory circuit by implanting dopant ions into the substrate 101 in the process step shown in FIG. 10F, the dopant ions should pass the edges of the memory gate structure 111. As a result, the tunnel insulating film 103 is partially damaged. For that reason, after the source/drain regions 112 and 113 have been defined, the memory gate structure 111 should be annealed if possible to repair the damage done on the tunnel insulating film 103.
But if this annealing process were conducted on the memory gate structure 111, the metal film 108 included in the memory gate structure 111 might be oxidized abnormally and even peel off unintentionally. Accordingly, there has been no other choice than omitting the annealing process. In that case, however, it is impossible to repair the damage done on the tunnel insulating film 103 and it is very hard for such a semiconductor memory device to show good reliability.
Also, where a resistor (not shown) should be formed out of the second polysilicon film 107 in the logic circuit section 200, the process step of removing part of the metal film 108 deposited on the second polysilicon film 107 should be performed additionally. Thus, the known method is disadvantageous in this respect also.
Furthermore, a hybrid device normally needs a greater area on the chip because a device of that type is essentially a combination of devices of two types. So the known structure interferes with the chip-downsizing trend.
An object of the present invention is to improve the reliability of a tunnel insulating film for a semiconductor memory device including memory and logic circuits on the same substrate and using a poly-metal gate structure for the logic circuit.
Another object of this invention is to reduce a chip area necessary for a semiconductor memory device of that type.
A third object of the invention is to get a resistor fabricated for a device of that type without increasing the number of process steps needed.
To achieve the first object, in the inventive process for fabricating a semiconductor memory device, it is not until a memory gate structure has been formed and annealed that a metal film, which will form part of a logic gate structure as a poly-metal gate, is deposited.
According to the present invention, a metal film to be contact pads for a storage element and a metal film that will form part of a logic gate structure are formed out of the same material in a single process step, thus accomplishing the second object.
The third object is also achievable by forming contacts that are self-aligned with a memory gate structure in accordance with the present invention. For that purpose, a sidewall insulating film, covering the side edges of contact pads in the memory circuit region, and an interlevel dielectric film are made of mutually different materials.
Specifically, a semiconductor memory device according to the present invention includes a memory circuit and a logic circuit that are formed on a single semiconductor substrate. The memory circuit includes a storage element having a memory gate structure. The memory gate structure includes: a tunnel insulating film formed on the substrate; and a control gate electrode formed out of a gate prototype film. The logic circuit includes a logical element having a logic gate structure. The logic gate structure includes: a lower gate electrode formed out of the gate prototype film; and an upper gate electrode formed out of a conductor film on the lower gate electrode. The conductor film contains a metal. In this memory device, the memory gate structure includes no metal films.
In the inventive semiconductor memory device, the memory gate structure includes no metal films, and the substrate can be annealed to repair the damage done on the tunnel insulating film. As a result, the tunnel insulating film can have its reliability improved. In addition, the logic gate structure includes the upper gate electrode formed out of a conductor film containing a metal. Accordingly, even if the logic gate structure is formed in a small size, the logic gate structure has a sufficiently low resistance.
In one embodiment of the present invention, the storage element preferably further includes a silicide film on the control gate electrode.
In another embodiment of the present invention, the storage element preferably further includes: source/drain regions; and contact pads that are electrically connected to the source/drain regions. The contact pads have preferably been formed out of the conductor film for the upper gate electrode. Then, the storage and logical elements can have their resistance and area both reduced without increasing the number of process steps needed. That is to say, the second object of the present invention is accomplished.
In this particular embodiment, the source/drain regions are preferably defined in parts of the substrate that are located beside the memory gate structure. And the contact pads preferably cover the upper surface of the source/drain regions and the side faces and upper edges of the memory gate structure.
Also, a first passivation film has preferably been formed on the upper surface of the control gate electrode, and a first sidewall insulating film has preferably been formed on the side faces of the control gate electrode. In this case, an etch selectivity of the first passivation film to the first sidewall insulating film is preferably sufficiently high.
Furthermore, the upper surface and side edges of the contact pads are preferably covered with a second passivation film and a second sidewall insulating film, respectively. The upper surface and side faces of the logic gate structure are also preferably covered with the second passivation and second sidewall insulating films, respectively. And the second passivation and second sidewall insulating films have been shaped out of first and second insulating films, respectively.
In this particular embodiment, an interlevel dielectric film has preferably been deposited as a third insulating film over the substrate. The first and second insulating films are preferably made of the same material. And an etch selectivity of the third insulating film to the first and second insulating films is preferably sufficiently high.
In still another embodiment, the inventive memory device may further include: an isolation region defined in the substrate; and a resistor formed on the isolation region. The resistor preferably includes: a body formed out of the gate prototype film; and two terminals, which have been formed out of the conductor film and make electrical contact with both edges of the body. Then, the third object of the present invention is achievable.
In yet another embodiment, the conductor film may be a single metal film, a stack of multiple metal films or a multilayer structure including a silicide film.
In yet another embodiment, a sidewall passivation film with an L-cross section and a first sidewall insulating film may have been stacked in this order on the side faces of the memory gate structure. On the other hand, the side faces of the logic gate structure may not be covered with the sidewall passivation film but with the first sidewall insulating film.
In yet another embodiment, the memory gate structure may further include a floating gate electrode and a capacitive insulating film that have been formed in this order on the tunnel insulating film and under the control gate electrode.
An inventive fabricating method is for use to fabricate a semiconductor memory device including a storage element and a logical element. The method includes the step of a) defining an isolation region in a semiconductor substrate and thereby partitioning the principal surface of the substrate into a memory circuit region where the storage element will be formed and a logic circuit region where the logical element will be formed. The method further includes the step of b) forming a first insulating film, a first gate prototype film of silicon and a second insulating film in this order on the memory circuit region of the substrate. The method further includes the steps of: c) forming a third insulating film on the logic circuit region of the substrate; d) depositing a second gate prototype film of silicon over the second and third insulating films; and e) forming a memory gate structure on the memory circuit region after the step d) has been performed. The memory gate structure includes a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode that have been formed by selectively etching away the first insulating, first gate prototype, second insulating and second gate prototype films, respectively. The method further includes the steps of: f) selectively implanting dopant ions into respective parts of the substrate that are located beside the memory gate structure, thereby defining source/drain regions for the storage element after the step e) has been performed; g) annealing the substrate after the step f) has been performed; h) depositing a conductor film, containing a metal, over the substrate as well as over part of the second gate prototype film located in the logic circuit region after the step g) has been performed; and i) forming a logic gate structure on the logic circuit region after the step h) has been performed. The logic gate structure includes a gate insulating film and lower and upper gate electrodes that have been formed by selectively etching away the third insulating, second gate prototype and conductor films, respectively.
In the inventive fabricating method, a control gate electrode is formed out of a second gate prototype film of silicon for a storage element. That is to say, the control gate electrode is not formed out of a metal film. Accordingly, a tunnel insulating film, which is formed out of a first insulating film, can be annealed to have its quality improved.
In one embodiment of the present invention, the substrate may be made of silicon, while the second gate prototype film may be made of polycrystalline or amorphous silicon. The method may further include the step of siliciding respective exposed silicon portions of the substrate and the control gate electrode after the step i) has been performed. Then, the storage and logical elements can both make good electrical contact with upper-level interconnects.
In another embodiment of the present invention, the inventive method may further include the steps of: depositing a fourth insulating film on part of the second gate prototype film located in the memory circuit region between the steps d) and e); and depositing a first sidewall insulating film on the side faces of the memory gate structure between the steps f) and h). The step e) may include forming a first passivation film out of the fourth insulating film on the control gate electrode in the memory circuit region. The step i) may include forming contact pads out of the conductor film while forming the logic gate structure. The contact pads are electrically connected to the source/drain regions for the storage element.
In this manner, while a logic gate structure is being formed, contact pads, which are electrically connected to source/drain regions for a storage element, are also formed out of a conductor film in accordance with the present invention. Thus, the second object of the present invention is achieved. In addition, the storage and logical elements can have their resistance and area both reduced without increasing the number of process steps needed.
In this particular embodiment, the contact pads preferably cover the upper surface of the source/drain regions and the side faces and upper edges of the memory gate structure.
Also, the inventive method preferably further includes the step of depositing a fifth insulating film over the conductor film between the steps h) and i). In that case, the step i) preferably includes forming a second passivation film out of the fifth insulating film on the upper gate electrode and on the contact pads.
More specifically, in the step i), after the second passivation film has been formed on the conductor film out of the fifth insulating film as a mask pattern for forming the logic gate structure and the contact pads, the conductor and first passivation films are preferably etched selectively to form the contact pads while the conductor, second gate prototype and third insulating films are preferably etched selectively to form the logic gate structure. The contact pads and the logic gate structure are both formed using the second passivation film as a mask. Generally speaking, when a fine-line pattern should be formed using a resist film as a mask, part of the resultant resist pattern might be deformed due to unwanted deposition of polymers produced from the resist film, thus possibly making it difficult to define the desired fine-line pattern. However, according to the present invention, a logic gate structure is formed using the fifth insulating film as a so-called xe2x80x9chard maskxe2x80x9d. Thus, the logic gate structure can be formed as a desired fine-line pattern.
In still another embodiment, the inventive method may further include the steps of: depositing a fourth insulating film on part of the second gate prototype film located in the memory circuit region between the steps d) and e); depositing a first sidewall insulating film on the side faces of the memory gate structure between the steps f) and h); depositing a fifth insulating film over the conductor film between the steps h) and i); selectively etching the fifth insulating film between the steps h) and i) to form a second passivation film that will be used as a mask pattern for forming the logic gate structure in the logic circuit region and that covers the memory circuit region entirely; and etching the second passivation, conductor and first passivation films using, as a mask, a resist pattern having an opening over the memory gate structure, thereby forming contact pads after the step i) has been performed. The contact pads are preferably electrically connected to the source/drain regions for the storage element. The step e) may include forming the first passivation film out of the fourth insulating film on the control gate electrode in the memory circuit region. In the step i), the logic gate structure may be formed using the second passivation film as an etching mask.
In this particular embodiment, the contact pads preferably cover the upper surface of the source/drain regions for the storage element and the side faces and upper edges of the memory gate structure.
Also, the fourth and fifth insulating films are preferably made of mutually different materials. Then, the etch selectivity of the fourth insulating film to be etched to the fifth insulating film used as a hard mask for forming the memory gate structure can be sufficiently high, thus considerably increasing the process stability.
Moreover, the substrate is preferably made of silicon while the second gate prototype film is preferably made of polycrystalline or amorphous silicon. And the method preferably further includes the step of siliciding respective exposed silicon portions of the substrate and the control gate electrode after the contact pads have been formed.
Furthermore, the second gate prototype film is preferably made of polycrystalline or amorphous silicon. And the method preferably further includes the steps of: implanting dopant ions into part of the second gate prototype film located in the logic circuit region between the steps d) and h); and implanting dopant ions into the logic circuit region of the substrate using the logic gate structure as a mask, thereby defining source/drain regions for the logical element and implanting the dopant ions into the control gate electrode after the contact pads have been formed.
In a dual-gate implantation process, ions of n- and p-type dopants are respectively implanted into the polysilicon gate electrodes of n- and p-channel transistors in the logic circuit region. In that case, when the substrate is annealed, the n- and p-type dopants introduced into those gate electrodes will cause interdiffusion, thus changing the threshold voltage of each of these transistors. However, according to the present invention, the unwanted phenomenon like that is avoidable without increasing the number of process steps.
Furthermore, the fourth insulating and first sidewall insulating films are preferably made of mutually different materials. Then, the etch selectivity of the fourth insulating film to the first sidewall insulating film can be so high that a contact for the control gate electrode can be formed just as intended.
Also, the inventive method may further include the step of forming a third passivation film out of the fourth insulating film on part of the second gate prototype film, where a resistor will be formed, between the steps d) and h). The third passivation film is used as a mask for defining the resistor. The second gate prototype film may be made of polycrystalline or amorphous silicon. The step d) may include covering part of the isolation region on which the resistor will be formed with the second gate prototype film. The step of forming the fourth insulating film may include covering part of the second gate prototype film where the resistor will be formed with the fourth insulating film. And the step i) may include forming a body of the resistor out of the part of the second gate prototype film, where the resistor will be formed, by etching the second gate prototype film using at least the third passivation film as a mask.
Then, the third object of the present invention is achieved. That is to say, where a resistor should be formed out of the second gate prototype film, there is no need to perform the additional process step of removing a metal film from a multilayer structure for a poly-metal gate. In addition, when the second gate prototype film is patterned to form a logic gate structure, the resistor is also formed at the same time. Accordingly, there is no need to perform the additional process step of forming the resistor.
Moreover, the inventive method may further include, after the contact pads have been formed, the step of: forming a second sidewall insulating film on the side edges of the contact pads along the length of the memory gate structure and on the side faces of the logic gate structure. The method may further include the step of implanting dopant ions into the logic circuit region of the substrate using the logic gate structure and the second sidewall insulating film as a mask, thereby defining source/drain regions for the logical element. The method may further include the step of depositing an interlevel dielectric film over the substrate. The interlevel dielectric film is preferably made of a material showing a high etch selectivity with respect to the second sidewall insulating film. And the method may further include the step of forming contact holes through the interlevel dielectric film so that the holes are located over, and self-aligned with, the contact pads and the source/drain regions of the logical element.
Then, a mask alignment margin, allowable for aligning the contact pads with a contact that should be located over the control gate electrode, can be increased considerably. As a result, the storage element can have its area further reduced.
In still another embodiment, the conductor film may be a single metal film, a stack of multiple metal films or a multilayer structure including a silicide film.
In yet another embodiment, the second insulating film may be a stack of oxide and nitride films.